The invention relates to an "R/2R" ladder circuit and technique for reducing the size and cost of an integrated circuit digital-to-analog converter.
The conventional practice of the prior art has been to provide the resistors in the MSB (most significant bit) portion of an R/2R ladder network which are ratio-matched as closely as possible, both with respect to resistance and physical structure, to corresponding resistors in the LSB (least significant bit) portion of the R/2R ladder. Typically, such resistors are formed of nichrome film or other resistive film composition having a sheet resistance of roughly 50 to 2000 ohms per square. Errors due, for example, to variations in semiconductor processing parameters such as the nichrome sheet resistance and mask/photoresist/etching-related processing parameters that occur in the MSB portions of the R/2R ladder have a much larger effect on the accuracy of the digital-to-analog converter than similar variations in the LSB portion. Consequently, the resistors in the MSB portion usually are laser trimmed during manufacture to precisely match the ratios of their desired resistances, but the resistors in the LSB portion usually are not trimmed, since these errors have a much smaller effect on digital-to-analog conversion accuracy. The digital-to-analog conversion accuracy depends more on precise resistance ratio matching of the resistances of the "R" and "2R" resistors of an R/2R ladder network than the absolute value of such resistances. Those skilled in the art know it is impractical to obtain both small absolute value errors and adequately close ratio-matching of resistances at the same time. Therefore, the circuits are designed such that the digital-to-analog conversion accuracy is based on obtaining accurate ratios, rather than absolute values, of resistances of the various resistors.
Typically, laser "trim tabs" are included as part of the nichrome film structure constituting each resistor in both the MSB and LSB portions of the R/2R ladder to obtain the required ratio matching, even though the laser trimming is performed only on the trim tabs in the MSB portion. Although resistors in the LSB portion of the R/2R ladder are not laser trimmed, it nevertheless has been necessary to provide trim tabs on the resistors in the LSB portion to achieve adequate ratio matching even though such untrimmed trim tabs substantially increase the amount of chip area and hence the chip cost.
Those skilled in the art know of another type of digital-to-analog converter, for example, as shown in FIG. 6, that uses switched, equal, constant current sources, instead of the above-mentioned voltage output type switched R/2R ladder technique. The MSB equal constant current sources are selected or deselected according to a thermometer code that represents a digital input word or a most significant group of bits thereof. A least significant group of bits of the digital input word can be utilized to switch a least significant group of equal constant current sources into a "non-switched" R/2R ladder network that performs binary current division to produce an analog output current representing the valued digital input word.
Referring to FIG. 6, the switched constant current circuitry 50 includes a number of NPN current source transistors 63-0,1,2 . . . 7, all having their bases connected to a reference voltage VEF2. The emitters of a most significant (MSB) group 63-4,5,6,7 of the NPN transistors are connected to a group of trimmable "MSB" resistors 52-1,2 . . . 4, each connected to a conductor 58 which receives a bias voltage V.sub.REF3. Each of the MSB resistors 52-1, . . . 4 has a trim tab and can be trimmed to provide a precise constant current I at the collector of each current source transistor. A trimmable scaling resistor 53, also having a trim tab, is connected between conductor 58 and a conductor 59. Note that the number of MSB transistors such as 63-4,5 . . . and associated emitter resistors such as 52-1,2 . . . depends on the number of binary bits of the digital input word D.sub.IN that are utilized to switch the constant current sources formed thereby. For example, if the 2 most significant bits of D.sub.IN are so utilized, then only 3 MSB transistors and associated emitter resistors are required. If the 3 most significant bits of D.sub.IN are so utilized, then 7 equal switched constant current sources are required. More generally, if N bits of D.sub.IN are to be so utilized, then 2.sup.N -1 MSB transistors and associated emitter resistors are required. Therefore, it is impractical to use more than three or four most significant bits of DN to switch equal constant current sources in a ladder network of a digital-to-analog converter. The most significant N bits of the digital input word D.sub.IN are decoded to produce the above mentioned thermometer code which switches the 2.sup.N -1 constant current sources.
A "LSB" group 63-0,1,2,3 of NPN transistors 63-0,1,2,3 have their bases connected to V.sub.REF2, and their emitters connected to the upper terminals of "LSB" resistors 51-0,1,2,3, respectively. Additional less significant NPN transistors could be included in the LSB group, as indicated by the dashed line extensions of the various horizontal conductors on the right side of FIG. 6. The lower terminals of LSB resistors 51-2 and 51-3 are connected to conductor 59. The MSB resistors 52-1,2,3,4 have a resistance R.sub.E. LSB resistors 51-2 and 51-3 are trimmable resistors, and also have a resistance of R.sub.E. LSB resistors 51-0 and 51-1 are coupled to the emitters of transistors 63-0 and 63-1, respectively, and to conductor 59, and have a resistance R.sub.E ' which is less than R.sub.E. Any additional less significant bit NPN transistors such as 63-0 and 63-1 and associated emitter resistors such as 51-0 and 51-1 are similarly connected to conductor 59 and have a resistance R.sub.E ', and are not trimmable. Constant equal currents I flow in the collectors of the LSB transistors 63-0,1,2,3 and any additional less significant NPN transistors.
The collectors of "MSB" transistors 63-4,5,6,7 are switched, according to corresponding bits of the digital input word, between a reference voltage V.sub.REF1 (which usually is at ground potential) and a current summing conductor 60 by means of switches 55-1,2 . . . 4 according to a thermometer code derived from the "MSB" bits of the digital input word. The collectors of transistors 63-0,1,2,3 are switched by the LSB bits of the digital input word to the various nodes of a "non-switched" R/2R ladder as shown.
The parameters and design trade-offs which determine the digital-to-analog conversion accuracy of the switched R/2R ladder network DAC to which the present invention relates are quite different from the parameters and design trade-offs which determine the digital-to-analog conversion accuracy of the switched constant current source DAC shown in FIG. 6. For example, switched current source digital-to-analog converters are subject to substantial variations in the current gains of the NPN transistors and in the base-to-emitter (V.sub.BE) voltages thereof. A complex, expensive reference voltage circuit indicated by a battery 64 in FIG. 6 producing a voltage equal to the difference between V.sub.REF2 and V.sub.REF3 is required to compensate for such current gain and V.sub.BE variations. The latter parameters constitute a very large portion of the digital-to-analog conversion error. For these and other reasons, switched equal current source digital-to-analog converters generally are not as accurate as switched R/2R digital-to-analog converters of approximately the same cost. Furthermore, the switched equal current source digital-to-analog converters generally require substantially more integrated circuit chip area and dissipate substantially more power than a digital-to-analog converter of comparable cost using a switched R/2R ladder network.
It would be desirable to provide a switched R/2R ladder structure and technique to reduce the physical size of the LSB portion of the R/2R ladder network by eliminating the trim tabs thereof, but without reducing the final accuracy of the digital-to-analog converter (DAC), multiplying digital-to-analog converter (MDAC), or any other circuit using an R/2R ladder.